In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
(a) Conversion condition
(b) Race around condition
(c) Lock out state
(d) Forbidden State
The question was asked in my homework.
This is a very interesting question from Master-Slave Flip-Flops in section Flip-Flops of Digital Circuits