A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.

A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.

(a) Right, one

(b) Right, two

(c) Left, one

(d) Left, three

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My question is from Universal Shift Registers topic in portion Registers of Digital Circuits

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A 4-bit shift register that receives 4 bits of parallel data will shift to the by position for each clock pulse.

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