Question

What is the worst case delay of the burst refresh in 4M by 1 DRAM?

(a) 0.4ms

(b) 0.2ms

(c) 170ns

(d) 180ns

I got this question during an interview.

I need to ask this question from DRAM Refreshing Techniques in chapter Memory Systems of Embedded Systems

Answer 1

Correct choice is (b) 0.2ms

For explanation I would say: A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that are, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.