Question

How instructions and data are accessed to pipeline stages of 80486 processor?

(a) Through internal unified cache

(b) Through external unified cache

(c) Through external cache

(d) Through multiple caches

I have been asked this question in a job interview.

This intriguing question comes from Features of Intel in division Embedded Processors of Embedded Systems

Answer 1

Right answer is (a) Through internal unified cache

Easiest explanation: In order to have instruction and data to the pipeline, the 80486 has an internal unified cache to contain both data and instructions. This helps in the independency of the processor on external memory.