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What type of timing is required for the burst interfaces?

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What type of timing is required for the burst interfaces?

(a) synchronous

(b) equal

(c) unequal

(d) symmetrical

I got this question in examination.

This intriguing question originated from Burst Interfaces topic in portion Memory Systems of Embedded Systems

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Right answer is (c) unequal

Explanation: The burst interfacing uses an unequal timing. It takes two clocks for the first access and only one for the remaining accesses which make it an unequal timing.

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