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How buffers are enabled in the parallel ports?

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How buffers are enabled in the parallel ports?

(a) by the data register

(b) by data direction register

(c) by individual control register

(d) by data and individual control register

I had been asked this question in homework.

My question comes from Parallel Ports topic in portion Basic Peripherals of Embedded Systems

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Right option is (b) by data direction register

To elaborate: The implementation of parallel port uses a couple of buffers which are enabled by the data direction register by setting the corresponding bit of the register.

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