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Which cycle can support the burst and single transfer mode?

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Which cycle can support the burst and single transfer mode?

(a) internal

(b) external

(c) both internal and external

(d) address cycle

I got this question in an internship interview.

Enquiry is from Implementation of DMA in division Basic Peripherals of Embedded Systems

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Right choice is (b) external

Explanation: The internal cycles can be programmed to occupy the partial or complete fulfillment of the available internal bus bandwidth while the external cycles provides support to the single transfer modes and burst mode.

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