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How many edges does the COOL use?

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How many edges does the COOL use?

(a) 1

(b) 2

(c) 3

(d) 4

I got this question in final exam.

Query is from Hardware or Software Partitioning topic in portion Implementing Embedded System: Hardware/Software Codesign of Embedded Systems

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Right option is (b) 2

The best explanation: The codesign tool has 2 edges. These are timing edges and the communication edges. The timing edge provides the timing constraints whereas the communication edge contains the information about the amount of information to be exchanged.

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