Question

Each unit to be modelled in a VHDL design is known as

(a) behavioural model

(b) design architecture

(c) design entity

(d) structural model

This question was posed to me in quiz.

My doubt stems from Introduction to VHDL in section Specification of Embedded Systems

Answer 1

Correct answer is (c) design entity

Best explanation: Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are two types of ingredients are used. These are the entity declaration and the architecture declaration.