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Which gate is used in the geometrical representation, if a single event causes hazards?

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in Embedded Systems by (271k points)
Which gate is used in the geometrical representation, if a single event causes hazards?

(a) AND

(b) NOT

(c) NAND

(d) OR

I have been asked this question by my college director while I was bunking the class.

Question is taken from Risk and Dependability Analysis in portion Validation of Embedded Systems

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Right choice is (d) OR

Easiest explanation: The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation if several events cause hazards.

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