The filtered digital signal is then decimated to
(a) reduce the rate of samples from fm to fs
(b) reduce the rate of samples from fs to fm
(c) increase the rate of samples from fm to fs
(d) increase the rate of samples from fs to fm
I have been asked this question during an online exam.
I need to ask this question from Sigma Delta ADC in chapter MSP430 Microcontroller of Microcontroller