Question

In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is integrated by the internal integrator for a fixed period of

(a) 256 clock cycles

(b) 1024 clock cycles

(c) 2048 clock cycles

(d) 4096 clock cycles

I got this question in unit test.

I need to ask this question from Interfacing Analog to Digital Data Converters in section Basic Peripherals and their Interfacing with 8086/88 of Microprocessor

Answer 1

Right choice is (c) 2048 clock cycles

To explain I would say: The internal integrator needs 2048 clock cycles to integrate voltage difference between input low and input high.