To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
(a) parallel
(b) serial
(c) both serial and parallel
(d) neither serial nor parallel
I have been asked this question by my school teacher while I was bunking the class.
I want to ask this question from Semiconductor Memory Interfacing topic in chapter Basic Peripherals and their Interfacing with 8086/88 of Microprocessor