The signal that is used to insert WAIT states in a bus cycle in 80386 is
(a) HOLD
(b) HLDA
(c) READY
(d) PEREQ
The question was posed to me in class test.
Enquiry is from Architecture and Signal Descriptions of 80386 in portion 32-bit Processors-80386, 80387 and 80486 of Microprocessor