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The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is

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The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is

(a) LTR

(b) INS

(c) CTS

(d) ESC

The question was asked in homework.

Question is taken from Protection topic in section 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor

1 Answer

0 votes
by (49.2k points)
Right choice is (d) ESC

The explanation: At the ESC instruction, the exception is generated, but the processor extension registers contain the address of failing instruction.

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