Question

For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of

(a) super pipelined technique

(b) multiple instruction issue

(c) super pipelined technique and multiple instruction issue

(d) none of the mentioned

This question was posed to me by my school teacher while I was bunking the class.

My enquiry is from Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction topic in section Recent Advancements in Microprocessor Architecture of Microprocessor

Answer 1

Right answer is (b) multiple instruction issue

To explain I would say: For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of multiple instruction issue.