The registers that are used to store four program controllable break point addresses are
(a) DR5-DR7
(b) DR0-DR1
(c) DR6-DR7
(d) DR0-DR3
I had been asked this question in examination.
I need to ask this question from Register Organisation of 80386 -2 topic in section 32-bit Processors-80386, 80387 and 80486 of Microprocessor