Question

In power down mode,

(a) Port pins maintain their logic levels

(b) SFRs maintain their logic levels

(c) Clock signal is disabled

(d) All of the mentioned

This question was posed to me at a job interview.

My doubt stems from Power Control Register in division Microcontroller 8051 of Microprocessor

Answer 1

Right choice is (d) All of the mentioned

Explanation: In power down mode, the clock signal is disabled and all the port pins and respective SFRs maintain their logic levels.