Question

All the interrupts at level 1 are polled in the second clock cycle of the

(a) forth T state

(b) fifth T state

(c) third T state

(d) none

I have been asked this question in a national level competition.

Asked question is from Interrupt Structure of 8051 topic in chapter Microcontroller 8051 of Microprocessor

Answer 1

Correct option is (b) fifth T state

Easiest explanation: All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.