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The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________

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The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________

(a) Parity error checking

(b) Ones catching

(c) Digital discrimination

(d) Digital filtering

I have been asked this question during an online exam.

Query is from Flip Flops in chapter Flip-Flops of Digital Circuits

1 Answer

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Right choice is (b) Ones catching

For explanation: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

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