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Where is trap vector table located in SPARC processor?

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Where is trap vector table located in SPARC processor?

(a) program counter

(b) Y register

(c) status register

(d) trap base register

I got this question in an interview.

My question is taken from The Sun SPARC RISC Model in division Embedded Processors of Embedded Systems

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The correct option is (d) trap base register

The best explanation: The trap vector table is located in the trap base register which supplies the address of the service routine. When it is completed REIT instructions are executed.

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