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Which level is an in-built nonmaskable interrupt in SPARC processor?

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Which level is an in-built nonmaskable interrupt in SPARC processor?

(a) 15

(b) 14

(c) 13

(d) 12

I got this question in an online interview.

I'm obligated to ask this question of The Sun SPARC RISC Model topic in portion Embedded Processors of Embedded Systems

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Right answer is (a) 15

For explanation: The level 15 of the SPARC processor is assigned to be a nonmaskable interrupt and the remaining 14 levels are unmasked and if necessary they can be made maskable.

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