Question

Which exception can be masked by clearing the EE bit to zero in the MSR?

(a) synchronous imprecise

(b) synchronous precise

(c) asynchronous imprecise

(d) asynchronous precise

I have been asked this question in exam.

The above asked question is from RISC Exceptions in chapter Interrupts and Exceptions of Embedded Systems

Answer 1

Right choice is (d) asynchronous precise

To explain: The asynchronous precise type exceptions can be masked by clearing the EE bits in the MSR. This bit is automatically cleared to zero in the MSR in order to prevent this interrupt causing an exception while other exceptions are being processed.