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The stage in which the CPU generates an address for data memory references in this stage is

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The stage in which the CPU generates an address for data memory references in this stage is

(a) prefetch stage

(b) D1 (first decode) stage

(c) D2 (second decode) stage

(d) execution stage

The question was asked by my school teacher while I was bunking the class.

I need to ask this question from System Architecture in division Recent Advancements in Microprocessor Architecture of Microprocessor

1 Answer

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Correct answer is (c) D2 (second decode) stage

The best explanation: In the D2 (second decode) stage, CPU generates an address for data memory references in this stage. This stage is required where the control word from D1 stage is again decoded for final execution.

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