The atleast number of machine cycles for which the external interrupts that are programmed level-sensitive should remain high is
(a) 1
(b) 2
(c) 3
(d) 0
I got this question by my school principal while I was bunking the class.
I would like to ask this question from Interrupt and Stack of 8051 -1 in section Microcontroller 8051 of Microprocessor