Question

Obtain the admittance of the last two elements in the parallel combination after transformation in the circuit shown below.

(a) 1+s

(b) 2+s

(c) 3+s

(d) 4+s

This question was posed to me during an internship interview.

My doubt is from Series and Parallel Combination of Elements topic in section S-Domain Analysis of Network Theory

Answer 1

Right choice is (d) 4+s

To explain I would say: The term admittance is defined as the inverse of impedance. The admittance of capacitor is 1/s and the admittance of resistor is 1/4 mho. So the admittance of the last two elements in the parallel combination is Y1(s) = 4 + s.