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In the following C.S. stage shown below, what is the output impedance if λ>0?

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In the following C.S. stage shown below, what is the output impedance if λ>0?

(a) ro

(b) 0

(c) R1

(d) R1 || ro

I got this question in unit test.

I would like to ask this question from MOSFET Amplifier with CS Configuration in section FET Amplifiers of Analog Circuits

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The correct option is (d) R1 || ro

Easy explanation: To find the output impedance, we perform a small signal analysis with the help of our rπ model. After placing every voltage source (Vcc and V1) to ground, we connect a simple voltage source at the drain node. Thereafter, the ratio of applied voltage to input current gives us the impedance looking into the drain which is ro. But this voltage will be applied in parallel to R1. Hence the total output impedance is R1 || ro.

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