Question

In the following C.S. stage, what is the gate voltage appearing across M1?

(a) V1 * [(R2 || R3) / (R1 || R2 || R3)]

(b) V1 * [(R2 + R3) / {R1 + R2) || R3}]

(c) V1 * [(R2 + R3) / (R1 + R2 + R3)]

(d) V1 * [(R2 || R3) / {R1 + (R2 ||R3}]

I got this question in final exam.

The above asked question is from MOSFET Amplifier with CS Configuration in chapter FET Amplifiers of Analog Circuits

Answer 1

The correct option is (d) V1 * [(R2 || R3) / {R1 + (R2 ||R3}]

For explanation I would say: The Thevenin resistance seen by the input voltage V1 is R1 + (R2 || R3). The Thevenin resistance is calculated by setting Vcc to 0 and hence calculating the current entering the C.S. stage. After finding the Thevenin Resistance, it is found that the voltage drop across the gate of M1 is due to a potential divider between R1 and (R2 || R3) where the voltage across (R2 || R3) is truly the gate voltage. Hence, the total gate voltage V1 is attenuated and becomes V1 * [(R2 || R3) / {R1 + (R2 ||R3}] .