Question

Which of the following is correct for a gated D-type flip-flop?

(a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW

(b) The output complement follows the input when enabled

(c) Only one of the inputs can be HIGH at a time

(d) The output toggles if one of the inputs is held HIGH

The question was asked during an interview for a job.

The doubt is from Flip Flops topic in section Flip-Flops of Digital Circuits

Answer 1

The correct answer is (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW

For explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.