Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
(a) Gated JK-latch
(b) Gated SR-latch
(c) Gated T-latch
(d) Gated D-latch
I have been asked this question during an internship interview.
Origin of the question is Flip Flops in chapter Flip-Flops of Digital Circuits