Question

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

(a) The clock pulse is LOW

(b) The clock pulse is HIGH

(c) The clock pulse transitions from LOW to HIGH

(d) The clock pulse transitions from HIGH to LOW

The question was posed to me during an interview for a job.

Enquiry is from Flip Flops in portion Flip-Flops of Digital Circuits

Answer 1

Correct option is (c) The clock pulse transitions from LOW to HIGH

Easy explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.