Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will __________

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will __________

(a) Continue to count with correct outputs

(b) Continue to count but have incorrect outputs

(c) Stop counting

(d) Turn into molten silicon

The question was posed to me in examination.

My doubt is from Counter Implementation and Applications topic in portion Counters of Digital Circuits

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Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will __________

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