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What is generated by an external interrupt in SPARC?

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What is generated by an external interrupt in SPARC?

(a) internal trap

(b) external trap

(c) memory trap

(d) interfaced trap

The question was posed to me in my homework.

Query is from The Sun SPARC RISC Model topic in section Embedded Processors of Embedded Systems

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The correct answer is (a) internal trap

The best explanation: In SPARC when an external interrupt is generated, an internal trap is created in the trap base register in which the current and next instructions are saved, the pipeline gets flushed and the processor turns into a supervisor mode.

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