If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the pin LOCK (active low) is
(a) low
(b) high
(c) low or high
(d) none of the mentioned
This question was posed to me in a national level competition.
My query is from Non Maskable Interrupt and Maskable Interrupt (INTR) topic in chapter Special Architectural Features and Related Programming of Microprocessor