Question

With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for

(a) 0 clock cycle

(b) 1 clock cycle

(c) 2 clock cycles

(d) 3 clock cycles

I have been asked this question in unit test.

Query is from Non Maskable Interrupt and Maskable Interrupt (INTR) in division Special Architectural Features and Related Programming of Microprocessor

Answer 1

The correct choice is (c) 2 clock cycles

The explanation: The INTA (active low) goes low and remains low for two clock cycles before returning back to the high state.