Question

A valid HOLD request is ascertained only after the completion of

(a) 34 clockcycles

(b) 24 clockcycles and 80286 is SET

(c) 34 clockcycles and 80286 is SET

(d) 34 clockcycles and 80286 is RESET

The question was asked in an online interview.

This intriguing question comes from Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence in division 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor

Answer 1

Right answer is (d) 34 clockcycles and 80286 is RESET

To explain: Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be ascertained.