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The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

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in Microprocessor by (39.4k points)
The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

(a) DEN

(b) DT/R (active low)

(c) MCE

(d) MB

I have been asked this question in my homework.

I'd like to ask this question from Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence in portion 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor

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by (49.2k points)
The correct option is (c) MCE

To explain: The MCE (Master Cascade Enable) signal of 82C288 enables the cascade address drivers during INTA cycles, to select the slave using the local address bus.

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