As a response to the valid bus hold request, the bus is pushed into
(a) TH (hold) state
(b) Ts (status) state
(c) Tc (command) state
(d) Ti (idle) state
The question was asked in class test.
My question comes from Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence in division 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor