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The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is

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The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is

(a) Prefetch stage

(b) D1 (first decode) stage

(c) D2 (second decode) stage

(d) Final stage

I got this question in an online quiz.

My question is taken from System Architecture in chapter Recent Advancements in Microprocessor Architecture of Microprocessor

1 Answer

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by (49.2k points)
The correct choice is (a) Prefetch stage

Explanation: In the prefetch stage of pipeline, the CPU fetches the instructions from the instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns the codes appropriately.

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