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After the micro-ops are issued by the microcode ROM, the control goes to

(a) trace cache

(b) front end branch predictor

(c) execution module

(d) instruction decoder

I had been asked this question during an online interview.

Question is from Features of Pentium 4, Netburst Microarchitecture For Pentium4 -1 topic in portion Pentium 4 processor of Microprocessor

1 Answer

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by (49.2k points)
Correct choice is (a) trace cache

To explain I would say: After the micro-ops are issued by the microcode ROM, the control goes to Trace cache once again. The micro-ops delivered by the trace cache and the microcode ROM are buffered in a queue in an orderly fashion.

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