Question

Which of the following is not a stage of pipeline of a RISC processor?

(a) read registers and decode the instructions

(b) fetch instructions from registers

(c) write result into a register

(d) access an operand in data memory

The question was posed to me in class test.

My doubt is from Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -2 in portion RISC Architecture of Microprocessor

Answer 1

Correct answer is (b) fetch instructions from registers

For explanation: There are 5 stages in pipelining. They are

1. Fetch instructions from memory

2. Read registers and decode the instructions

3. Execute the instructions or calculate an address

4. Access an operand in data memory

5. Write result into a register.