Question

What is an ambiguous condition in a NAND based S’-R’ latch?

(a) S’=0, R’=1

(b) S’=1, R’=0

(c) S’=1, R’=1

(d) S’=0, R’=0

I had been asked this question during an interview.

I'd like to ask this question from Flip Flops topic in section Flip-Flops of Digital Circuits

Answer 1

Right choice is (d) S’=0, R’=0

Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.