Question

The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

(a) 1

(b) 2

(c) 3

(d) 4

I have been asked this question by my school principal while I was bunking the class.

This question is from Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence in section 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor

Answer 1

Right option is (c) 3

Best explanation: The 80286 allows three idle states (Ti) between the two INTA cycles, to meet the 8259A speed and cascade address output delay.