The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of
(a) first INTA (active low) pulse from 80286
(b) second INTA (active low) pulse from 80286
(c) third INTA (active low) pulse from 80286
(d) none of the mentioned
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I'm obligated to ask this question of Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence in division 80286-80287-A Microprocessor with Memory Management and Protection of Microprocessor